SkyWater 130nm MPW Shuttle Tapeout Guide

Actionable step-by-step plan for submitting the Muon HBM4 Series IP netlist to open silicon shuttle programs.

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1. What is an MPW Shuttle?

A Multi-Project Wafer (MPW) shuttle enables chip designers to share wafer manufacturing costs. Instead of paying $1M+ for a dedicated mask set, a shuttle run delivers physical silicon test chips for $10k to $20k (or free via Google/Efabless research grants).

Foundry Prototype Phase
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2. Physical Silicon Deliverables

When the foundry run completes in Minnesota, USA (12–16 weeks):

  • ✔️ 10 to 50 Packaged IC Chips (QFN or LGA packaging)
  • ✔️ Evaluation Breakout PCB Board with test socket
  • ✔️ USB-to-SPI/APB Debug Interface for direct Mac testing

3. Command Sequence for Shuttle Integration

Step A: Clone Efabless Caravel user project template and integrate synthesized netlist:

# Clone Caravel User Project harness repository
git clone https://github.com/efabless/caravel_user_project.git hbm4_shuttle
cd hbm4_shuttle

# Copy synthesized netlist & OpenLane configuration
cp -r /path/to/hbm4_custom/openlane/hbm4_custom_top openlane/
cp /path/to/hbm4_custom/openlane/hbm4_custom_top_netlist.v verilog/rtl/

Step B: Run automated KLayout DRC & Magic LVS precheck verification:

# Run Efabless precheck verification suite
make precheck